Physical Design interview questions - Part 4

  1. What are all the SDC checks?
  2. What is zero wire load model (ZWLM)?
  3. What if you see issues during sanity checks?
  4. What is meant by push-down floor plan, what are contents of a pushdown file?
  5. What was the shape of your block?
  6. Is your block top down or bottom up?
  7. How many ports you had in your design? (both Input and output).
  8. What was the layers assigned to those ports in your design?
  9. What was the width and spacing of the port in your design?
  10. What was the width and spacing of the clock port in your design?
  11. How many layers has been assigned to the ports in your design?
  12. What is meaning of stacked IO ports?
  13. How do you calculate your die size?
  14. What was your starting core and std cell utilization?
  15. What is blockage, explain placement, routing blockages?
  16. What was the placing between the macros you have kept?
  17. If you rotate the macros? If so then what kind of macros are they?
  18. If you have any AMS macros (PLL) if so what extra precautions you took while placing and routing?
  19. What is difference between std call and macros?
  20. How many layers are used for macros?
  21. How many layers are used for std cells?
  22. Explain pg structure of std cells and macros?
  23. How do you place the macros?
  24. Explain macro flow guideliness?
  25. What is fly line analysis?
  26. What is mean by data flow diagram?
  27. What will you do if IO port density is high in a particular location?
  28. What is feed through?
  29. How will you perform feed through analysis?
  30. What will you do if starting utilization is very high?
  31. Your netlist area is grown much more than expected then what will you do.
  32. What is do not use & do not touch cells?
  33. Who will provide list of those cells and why they are being marked as do not use?
  34. What kind of macros you had in your design and how many pins are there and what layers signal and power pins were?
  35. How do you calculate the channel width? What was the channel width you have used in the design?
  36. What will you do if you have congestion between the macros?
  37. How do you differentiate std cells and macros in the tool?
  38. What is power routing?
  39. What was the power nets names in your design?
  40. What is mean by direct PG connection and why do we need to do it?
  41. What layers you have used for power routing?
  42. What is stack via?
  43. Explain power routing structure?
  44. What is RDL layer (topmost layer)?
  45. How will you plan your channels, what are the basic things you have to look at while planning channels?
  46. How do you verify if there are pg open and short?
  47. What will you do if you find pg open?
  48. Setup time equation?
  49. Hold time equation?
  50. Differences between flop and a latch?