Physical Design interview questions - Part 8

  1. What is signal integrity? How does it affect Timing?
  2. What is IR drop? How does affect timing?
  3. What is EM and Antenna effects?
  4. What is floor plan and power plan?
  5. What are types of routing?
  6. What is a grid. Why do we different types of grids?
  7. What is core and how will you decide w/h ratio for core?
  8. What is effective utilization and chip utilization?
  9. What is latency? Give the types?
  10. What is LEF?
  11. What is DEF?
  12. What are the steps involved in designing an optimal pad ring?
  13. What are the steps that you have done in the design flow?
  14. What are the issues in floor plan?
  15. How can you estimate area of block?
  16. How much aspect ratio should be kept (or have you kept) and what is the utilization?
  17. How to calculate core ring and stripe widths?
  18. What if hot spot found in some area of block? How you tackle this?
  19. Even after adding stripes if you have hot spot what you do?
  20. What is threshold voltage? How it affect timing?
  21. What is content of lib, lef, sdc?
  22. What is meant my 9 track, 12 track standard cells?
  23. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
  24. What is setup and hold? Why there are? What if setup and hold violates?
  25. In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
  26. How R and C values are affecting time?
  27. How ohm (R), fared (C) is related to second (T)?
  28. What is transition? What if transition time is more?
  29. What is difference between normal buffer and clock buffer?
  30. What is antenna effect? How it is avoided?
  31. What is ESD?
  32. What is cross talk? How can you avoid?
  33. How double spacing will avoid cross talk?
  34. What is difference between HFN synthesis and CTS?
  35. What is hold problem? How can you avoid it?
  36. For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
  37. What is partial floor plan?
  38. What parameters (or aspects) differentiate Chip Design & Block level design??
  39. How do you place macros in a full chip design?
  40. Differentiate between a Hierarchical Design and flat design?
  41. Which is more complicated when u have a 48 MHz and 500 MHz clock design?
  42. Name few tools which you used for physical verification?
  43. What are the input files will you give for primetime correlation?
  44. What are the algorithms used while routing? Will it optimize wire length?
  45. How will you decide the Pin location in block level design?
  46. If the routing congestion exists between two macros, then what will you do?
  47. How will you place the macros?
  48. How will you decide the die size?
  49. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
  50. If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?