Physical Design interview questions - Part 1

Physical Design interview questions - Part 1

  1. How will you make sure that your power structure is good?
  2. Why we are following certain guidelines for macros placement and what are those guidelines?
  3. What is the minimum space required in between macros if channel is there in non-pin side of macros?
  4. What is the distance between tap cells in your design?
  5. How you will perform cell spreading in placement if congestion is there?
  6. Tell me about 2-pass approach in placement.
  7. Why we are not taking care about hold violations at placement stage?
  8. What are differences between OCV and POCV?
  9. What are the different ways to fix setup and hold? Which one is difficult to fix setup? Or hold?
  10. Which violation you will fix first? Is it setup or hold?
  11. How will you improve your insertion delay?
  12. What happens if you place macros at the centre?
  13. If there the situation that you have to place the macro at the centre then techniques to reduce the issues like congestion and timing?
  14. What issues you faced when you are in placement stage? and how you fix them
  15. Why you will check setup in placement stage and why you will check hold after cts?
  16. Placement optimization techniques?
  17. Write setup and hold equations?
  18. Techniques to fix setup and hold?
  19. If you have optimize the design but still you have setup violations how you will fix them?
  20. What is CTS?
  21. What is Clock tree specification file?
  22. How do you know the time slack Is acceptable to go next stage?
  23. What def file consists of?
  24. What LEF file consists of?
  25. What is crosstalk?
  26. What are ndr rules? Why we want to apply them?
  27. What is difference between clock buffer and normal buffer?
  28. If buffer and inverter are there which one is preferable?
  29. What is latency?
  30. What are the inputs for LVS?
  31. What is metal pitch?
  32. What is multi cycle path?
  33. What is OCV AND AOCV?
  34. Do you know anything about DPT?
  35. What are the contents of SDC file?
  36. If one path have both setup and hold violations? How you will fix that path?
  37. Did you known about negative and positive skew? Briefly can you tell about that?
  38. What is the difference between flat and hierarchical get_cells count?
  39. Which is more complicated when u have a 48 MHz and 500 MHz clock design?
  40. How do you place macros in a full chip design?
  41. What parameters (or aspects) differentiate Chip Design and Block level design?
  42. If the routing congestion exists between two macros, then what will you do?
  43. If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
  44. How to calculate core ring width, macro ring width and strap or trunk width?
  45. How to find number of power pad and IO power pads?
  46. How the width of metal and number of straps calculated for power and ground?
  47. What are the problems faced related to timing?
  48. During power analysis, if you are facing IR drop problem, then how did you avoid?
  49. Define antenna problem and how did you resolve these problem?
  50. How delays vary with different PVT conditions? Show the graph.