Physical Design interview questions - Part 2

Physical Design interview questions - Part 2

  1. What is IR drop? How to avoid? How it affects timing?
  2. What is EM and it effects?
  3. What is latency? Give the types.
  4. What is congestion?
  5. What is cloning and buffering?
  6. Do you know about input vector controlled method of leakage reduction?
  7. How can you reduce dynamic power?
  8. If you have both IR drop and congestion how will you fix it?
  9. Is increasing power line width and providing more number of straps are the only solution to IR drop?
  10. How will you decide best floorplan?
  11. In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?
  12. How will you synthesize clock tree?
  13. What is cross talk? How can you avoid cross talk?
  14. How shielding avoids crosstalk problem? What exactly happens there?
  15. Why double spacing and multiple vias are used related to clock?
  16. How buffer can be used in victim to avoid crosstalk?
  17. What are High-Vt and Low-Vt cells?
  18. What is useful-skew?
  19. What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?
  20. What is latch up in CMOS design and ways to prevent it?
  21. What is the difference between core filler cells and metal fillers?
  22. What is meant by ATPG?
  23. What is meant by clock skew and how can it be avoided?
  24. Why is Hold time neglected while calculating Max Frequency? Why only Setup time is considered?
  25. What is capacitive loading? How does it affect slew rate?
  26. What is meant by virtual clock definition and why do i need it?
  27. What are the various Design constraints used while performing Synthesis for a design?
  28. What are set up time and hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
  29. What is difference between setup and hold time?
  30. Hold time does not depend on clock. Is it true? If so why?
  31. What is false path? How it is determined in circuit?
  32. How power is related with clock frequency?
  33. Is it possible to reduce clock skew to zero?
  34. What is skew, what are problems associated with it and how to minimize it?
  35. What is the significance of contamination delay in sequential circuit timing?
  36. What is wire load model?
  37. Who provides the DRC rules?
  38. What is LVS and why do we do that?
  39. Define antenna problem and how did u resolve these problem?
  40. What is signal integrity? How it affects Timing?
  41. What is .lib, LEF, DEF, .tf?
  42. What are DFM issues?
  43. What is meant my 9 track, 12 track standard cells?
  44. What is threshold voltage? How it affect timing?
  45. What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
  46. How R and C values are affecting time?
  47. What is ESD?
  48. What is difference between normal buffer and clock buffer?
  49. What is difference between HFN synthesis and CTS?
  50. For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?