Physical Design interview questions - Part 3

Physical Design interview questions - Part 3

  1. Why is Extraction performed?
  2. Explain the various Capacitances associated with a transistor and which one of them is the most prominent?
  3. What is clock feed through?
  4. Why are the minimum pulse width and minimum period checks important during timing analysis?
  5. Why does the pulse width of the signal shrink?
  6. Why is the insertion delay high? What could be the reason?
  7. What is the difference between set_false_path & set_disable_timing?
  8. Skew is not getting balanced, what could be the reason?
  9. Clock-tree is not getting built for certain sinks, what could be the reason?
  10. What kind of Vt cells you will use in clock-tree? Can we mix the Vt in the clock-tree?
  11. Explain PD flow?
  12. What are all your inputs?
  13. What is netlist?
  14. What is SDC and contains of SDC with the explanation of command with the diagram?
  15. What is the library?
  16. What are the different file format inside a library and contains them?
  17. What are tech file and contains of tech file?
  18. If we change the process what is the effect of that on .tech file.
  19. What are the technologies you know and use?
  20. What are the different process.(28lp,28HP,28GP,28HPC,28HPC+,28HPM)?
  21. What is unit tile parameter inside tech file?
  22. What is the meaning of fat table spacing in the tech file?
  23. What means by via rule inside tech file?
  24. What is metal density rule, why it is important?
  25. What is TLU+ file? What is there inside TLU+, what value do you see inside TLU+ files?
  26. Is TLU+ human re-able?
  27. What is there in a physical library?
  28. What are the different view we call them as physical library.(lef,fram)
  29. Draw layout for NAND, NOR?
  30. What is present inside a lef file?
  31. What is the meaning of track?
  32. What is the meaning of the placement grid?
  33. What is the meaning of std cell height?
  34. What is meant by 8-track, 10-track, and 12-track? Can we mix 8, 10 and 12 tracks in the same design?
  35. What is .lib, how a cell delay is calculated?
  36. What is the meaning of 7X7 table, have you come across 7X7, 5X5, 9X9 tables? Why are we choosing 7X7?
  37. What kind of power is captured inside .lib?
  38. What is the meaning of cell rise and cell fall in .lib?
  39. What is the meaning of rise transition and fall transition?
  40. What is meaning of drive strength?
  41. What is meaning of multi Vt library?
  42. What is meant by timing arc?
  43. What the meaning of timing unate?
  44. What is PVT? How does delay vary with PVT? What are the different PVT corners you are aware of?
  45. What is temp inversion?
  46. What will you do once you receive all the inputs?
  47. What is the need of the sanity check?
  48. What are the different checks you perform during sanity checks?
  49. Can the output and input be floating?
  50. What will happen if op and pg are connected?