Physical Design interview questions - Part 5

Physical Design interview questions - Part 5

  1. What are different ways to fix a setup time violation?
  2. What are different ways to fix a hold time violation?
  3. What is GBA analysis?
  4. What is the difference between GBA and PBA analysis?
  5. What is AOCV?
  6. What is POCV?
  7. Explain the concept of statistical OCV?
  8. What is a ring oscillator, how do you determine the frequency of a ring oscillator?
  9. What is CRPR?
  10. Single cycle path, multicycle path, false path, zero cycle path differences?
  11. Write the constraints for a multicycle path of 3 and zero cycle path?
  12. Setup and hold constraint equations for multicycle path, zero cycle path?
  13. Explain IO budgeting?
  14. What is Antenna effect?
  15. What is crosstalk?
  16. Different methods to minimize clock crosstalk?
  17. Should we fix data crosstalk?
  18. How does crosstalk affect setup timing and hold timing?
  19. Which cells among HVT, SVT, LVT cells have more variation w.r.t. P, V, T?
  20. What is a lockup latch, explain its applications?
  21. Why should we add a lockup latch?
  22. How many timing corners you sign-off your chip?
  23. How to design and write Verilog code for asynchronous FIFO
  24. Why do we need a FIFO?
  25. What are the differences between SRAM and DRAM?
  26. What is the difference between a latch and a flip-flop?
  27. What is metastability? How to fix this problem?
  28. What is a source synchronous clocking scheme?
  29. Design a circuit to divide an incoming clock by 2?
  30. Design a circuit to divide an incoming clock by 3?
  31. Why is interconnect not scaling as well as transistors?
  32. What is clock jitter? Source jitter and network jitter?
  33. Relationship between master clock and generated clock?
  34. Why do we need generated clocks?
  35. What is the output of an inverter if the VDD and VSS connections are swapped?
  36. What is zero-wire-load timing?
  37. What are various clock tree structures?
  38. What are the advantages, disadvantages of clock tree, H-tree, clock mesh?
  39. What is power gating?
  40. What is clock gating?
  41. What is an ICG?
  42. How do you model the fan-out of an ICG in synthesis?
  43. Explain the concept of MCMM (Multi-Corner-Multi-Mode)?
  44. What is leakage power, dynamic power and internal power?
  45. How to reduce leakage power, dynamic power and internal power?
  46. What is Elmore delay model?
  47. Compute the delay of an RC tree using Elmore delay model
  48. What is power grid? What stage of the design steps is it planned?
  49. Hierarchical design planning, what complexities get added on when we split a big design into blocks?
  50. What is a level shifter, retention flop?