Physical Design interview questions - Part 6

Physical Design interview questions - Part 6

  1. How do you sign-off static IR drop and dynamic IR drop?
  2. How to minimize addition of hold buffers?
  3. Write Verilog code for a regular encoder and a priority encoder
  4. What is JTAG?
  5. What is mBIST?
  6. If you have 10,000 DRC violations on a post-route database, what would be your
  7. Approach to fix these violations?
  8. Design AND, OR and NOT gates using Mux?
  9. How to fix glitch violations?
  10. What is Multi-Input-Switching (MIS)?
  11. How to margin for MIS in timing constraints?
  12. What is a Transition Delay Fault?
  13. A chip fails to function when it boots up, however, as the temperature is increased, it
  14. Starts to operate correctly, what could be the reason for it?
  15. What are Decap cells? What is the purpose of it?
  16. How to select SRAM macro cells for design?
  17. What is a CCS timing model? What deficiencies are addressed from a NLDM timing Model?
  18. Why should we sign-off max_trans and max_cap violations before chip tape out?
  19. What is miller cap?
  20. What is temperature inversion?
  21. Write a TCL script to find if two rectangles overlap
  22. What are the differences between moore and mealy models?
  23. Differences between logically exclusive, physical exclusive, asynchronous clock groups
  24. Clock gating checks?
  25. Setup hold checks?
  26. How do planar transistors and FinFets differ? Which transistors will have more Performance and why?
  27. What is DIBL effect?
  28. What is double patterning?
  29. What are various techniques to fix a timing violation explain with examples
  30. What is the impact of dummy fill on timing?
  31. What are the different techniques to mitigate congestion in a design?
  32. What is cell padding?
  33. What is congestion driven restructuring?
  34. What are various synchronization techniques in clock domain crossings
  35. How to achieve correlation between PnR and sign-off timing
  36. How to achieve correlation between synthesis and PnR
  37. When you have a path with all combinational gates and it is violating by a big number after synthesis, there is no scope to upsize or VT swap, what will you do?
  38. What are the various techniques to decrease clock skew?
  39. What is useful skew?
  40. What is time borrowing when you use latches?
  41. Is NDR better or shielding better for clock tree synthesis?
  42. The blocks are timing clean and when integrated at top-level there are lot of setup and hold violations. What are all the possible causes of these new violations?
  43. What is DVFS?
  44. Which design is more complicated 10MHZ or 100MHz?
  45. What are the power gating cells?
  46. What is HFNS (high fan-out net synthesis)?
  47. What is Electro migration (EM)?
  48. Why NAND gate is preferred than NOR?
  49. What is isolation cell?
  50. What is retention flop?