Physical Design interview questions - Part 7

Physical Design interview questions - Part 7

  1. What is MMMC (multi-mode multi corner)?
  2. What are the guidelines for macro placement?
  3. What are the sanity checks in pd?
  4. What is the difference between Halo and Blockage?
  5. Why we apply NDR rules before routing?
  6. What are the types of blockages?
  7. How to fix congestion?
  8. How will you reduce congestion near I/O ports?
  9. What are routing grids?
  10. Why derates are used for timing calculations? Is it good or bad?
  11. What are several factors to improve propagation delay of standard cell?
  12. How delays are characterized using WLM (Wire Load Model)?
  13. What are various techniques to resolve congestion/noise?
  14. How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?
  15. What are pros/cons of latch/FF (Flip Flop)?
  16. What are various formal verification issues you faced and how did you resolve?
  17. How do you calculate maximum frequency given setup, hold, clock and clock skew?
  18. What are effects of metastability?
  19. Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
  20. How to solve cross clock timing path?
  21. How to determine the depth of FIFO/ size of the FIFO?
  22. What are the challenges you faced in place and route, FV (Functional Verification), ECO (Engineering Change Order) areas?
  23. Explain ECO (Engineering Change Order) methodology.
  24. Explain CTS (Clock Tree Synthesis) flow.
  25. What kind of routing issues you faced?
  26. How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?
  27. What were your design skew/insertion delay targets?
  28. How is IR drop analysis done? What are various statistics available in reports?
  29. Explain pin density/ cell density issues, hotspots?
  30. In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
  31. Can a single port have multi-clocked? How do you set delays for such ports?
  32. How is scan DEF (Design Exchange Format) generated?
  33. What is purpose of lockup latch in scan chain?
  34. Explain short circuit current.
  35. How do you set inter clock uncertainty?
  36. What is trade off between dynamic power (current) and leakage power (current)?
  37. Explain top level pin placement flow? What are parameters to decide?
  38. With net length of 1000um how will you compute RC values, using equations/tech file info?
  39. What do noise reports represent?
  40. How to analyze clock tree reports?
  41. In equivalence checking, how do you handle scanen signal?
  42. Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic. Which path is fastest path to have hold violation and how will you resolve?
  43. Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse width.
  44. How will you decide the Pin location in block level design?
  45. If the routing congestion exists between two macros, then what will you do?
  46. What is meant my 9 track, 12 track standard cells?
  47. In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
  48. What is transition? What if transition time is more?
  49. How do you compute net delay (interconnect delay) / decode RC values present in tech file?
  50. Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?