Physical Design interview questions - Part 10

Physical Design interview questions - Part 10

  1. If you have 10,000 DRC violations on a post-route database, what would be your approach to fix these violations?
  2. Design AND, OR and NOT gates using Muxes
  3. How to fix glitch violations?
  4. What is Multi-Input-Switching (MIS)?
    1. How to margin for MIS in timing constraints?
  5. What is a Transition Delay Fault?
  6. A chip fails to function when it boots up, however, as the temperature is increased, it starts to operate correctly, what could be the reason for it?
  7. What are Decap cells? What is the purpose of it?
  8. How to select SRAM macro cells for design?
  9. What is a CCS timing model? What deficiencies are addressed from a NLDM timing model?
  10. Why should we sign-off max_trans and max_cap violations before chip tapeout?
  11. What is miller cap?
  12. What is temperature inversion?
  13. Write a TCL script to find if two rectangles overlap
  14. FSM design questions
  15. What are the differences between moore and mealy models?
  16. Differences between logically_exclusive, physical_exclusive, asynchronous clock groups
  17. Clock gating checks
  18. How do planar transistors and FinFets differ? Which transistors will have more Performance and why?
  19. What is DIBL effect?
  20. What is double patterning?
  21. What are blocking and non-blocking assignments in verilog? Details of both these Statements
  22. What are various techniques to fix a timing violation?
  23. State machine to divide the clock by 3/2
  24. Two cube calendar puzzle
  25. What is the impact of dummy fill on timing?
    1. How does it affect setup and hold timing
  26. What are the different techniques to mitigate congestion in a design?
    1. What is cell padding?
    2. What is congestion driven restructuring?
  27. Explain the concepts of throughput and latency
  28. What is cache miss?
  29. What is pipelining?
  30. Differences between asynchronous reset and synchronous reset
  31. What is a reset synchronizer?
  32. What are various synchronization techniques in clock domain crossings?
  33. What is Moore’s law and Dennard Scaling?
  34. What is multi-bit flip-flop? What are the advantages, disadvantages using them in Synthesis?
  35. How to achieve correlation between synthesis and PnR?
    1. How to achieve correlation between PnR and sign-off timing?
  36. When you have a path with all combinational gates and it is violating by a big number after synthesis, there is no scope to upsize or vt swap, what will you do?
  37. What is ECC correction in memories, how is it different from parity? What are the pros and cons of these techniques?
  38. What are the various techniques to decrease clock skew?
  39. What is useful skew?
  40. Write setup and hold timing equations for a T-Flip-Flop
  41. Difference between array and dictionary in TCL programming language
  42. How will you fix AC EM violations during chip closure?
  43. What are stuck-at-faults?
  44. Design a circuit to generate Fibonacci numbers?
  45. Design a clock mux for glitch free clock switching?
  46. Design a XOR gate using NAND gates?
  47. What is time borrowing when you use latches?
  48. What is FO4 (Fan-out-of-4)?
  49. Can there be negative hold time? Explain a scenario/circuit resulting in negative hold time requirement?
  50. Can setup requirement time be negative? Explain.