Physical Design interview questions - Part 12

Physical Design interview questions - Part 12

  1. How do you calculate maximum frequency given setup, hold, clock and clock skew?
  2.  Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
  3. How to solve cross clock timing path?
  4. In StarRC, what is "Un-annotated Nets”? Is it ok to proceed with the SPEF that contains un-annotated nets?
  5. How do you fix setup and hold violations in scan mode?
  6. What are min-density rules and why do we need them?
  7. In which scenario (best,typ,worst) you will run power optimization. Justify your answer.
  8. Explain IR drop analysis and in which scenario (best,typ,worst) you will run IR drop analysis? Justify your answer.
  9. What is an Isolation cell? What are the types of isolation cell and how you choose which cell to add?
  10. Which check is frequency independant, setup or hold? Have you heard of frequency dependant hold check?
  11. What is ERC?
  12. What is the difference between graph based and path based analysis? 
  13. What are the different physical only cells and why do we need them?
  14. Say after CTS, your skew target is met but your latency is more than the expected, is it ok to proceed? Justify your answer.
  15. Did you use clock buffer or clock inverter in your design and why?
  16. What is a multi cycle path? For a multi cycle path of 4 cycles, on which cycle edge do setup and hold check occur?
  17. What is the difference between 9T and 12T cells in terms of area, performance and power?
  18. What is max_fanout constraint? Say your design's timing is fine but you have at least one (or more) max_fanout violation. Is it ok to tape out the design without clearing the max_fanout violation?
  19. How do you arrive at max_transition constraint value?
  20. What is max_trans constraint? Say your design's timing is fine but you have at least one (or more) max-tran violation. Is it ok to tape out the design without clearing the max_transition violation? 
  21. A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I go about it?
  22. How to do floorplanning for multi vdd designs?
  23. How to control via generation when do special route for standard cells, such how to preserve gaps between vias for other net routing?
  24. What actually happens in power planning? What is the main aim of power planning?
  25. How power stripes are useful in power planning?
  26. What are the different ways in which antenna violation can be prevented?
  27. What is the function of tie-high and tie-low cells?
  28. What are the changes that are provided to meet design power targets?
  29. What are the different measures that are required to achieve the design for better yield?
  30. What are the different classification of the timing control?
  31. Why not inductance in cmos design?
  32. What are the input files required to run STA?
  33. What’s the information present in these files which helps for delay calculation?
  34. What’s the different between Crosstalk and without crosstalk based STA analysis.
  35.  In the Hierarchical design, there are different Blocks. How are we capturing the timing information of those blocks in our design?
  36.  What’s the difference between PVT corner and RC corners?
  37. What’s the main difference between OCV and AOCV?
  38. What are the different reasons for high voltage drop in design?
  39. How to find high IR drop is due to high impedence?
  40. What is the impact of width variation of a wire on resistance?
  41. Difference between Vector and Vectorless analysis?
  42. What is the impact of temperature on resistance?
  43. In what form package is contributing to IR drop, give formula only for total drop?
  44. What is the flow for Power and IR drop analysis?
  45. What are the causes for Static and Dynamic issues?
  46. Mention solution for Static and Dynamic IR drop issues?
  47. What is the issue we will see if a wire’s current requirement is very high than its capacity?
  48. What factor causes ESD issues?
  49. What is the use of switch cells, how those are placed in the design?
  50. What is the formula for Switching Power?