Physical Design interview questions - Part 13

Physical Design interview questions - Part 13

  1.  What are SDC, how do you decide that a path is a false path?
  2. What is max transition? How you decide that value?
  3. How do you set max output load (based on what factors?)
  4. What are the inputs to Prime Time?
  5. What does you do for low power design?
  6. What are retention registers?
  7. What are HVT cells, how area increases with HVT cells?
  8. What does CTS do for routing clocks? Global routing..?
  9. How global routing is different from detailed routing?
  10.  How GR will handle congested paths, what is its impact on delay?
  11. What is single case, worst case and best case and OCV analysis?
  12. How can one library have many values for same input slew and output load?
  13. Will you give constraints for via in CTS or not. How vias will affect the clock routing?
  14. Do you know about input vector controlled method of leakage reduction?
  15. Methods of leakage reduction? 
  16. Is increasing power line width and providing more number of straps are the only solution to IR drop? 
  17. If you import a LEF for a macro and you find out that the macro pins are moved from boundary to centre, what will be your approach?
  18. What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
  19. Why metal density rules are important?
  20. Why power stripes routed in the top metal layers?
  21. Did you get Antenna problem in your project for all the metal layers? How did you fix them?
  22. How do you reduce power dissipation using High Vt and Low Vt on your design?
  23. What are the various statistics available in IR drop reports?
  24. What is the importance of IR drop analysis?
  25. What is the difference between ndm generation using oas and using lef?
  26. Discuss the steps involved in Layout versus Schematic?
  27. Define ERC?
  28. What are the Sign checks after generating layout?
  29. What are the different inputs of extraction tool?
  30. What are the different types/Formats of output of the Extraction Tool or the Parasitic Data?
  31. What type of information, we can obtain after running the extraction tool?
  32. For coupling cap and ground cap- is there different dielectric constant or it’s same? If it’s different why?
  33. In lower technology, coupling capacitance is always a challenge. For reducing the coupling capacitance what technique we are using right now?
  34. What is the difference between 40nm & 7nm?
  35. What is the difference between refine placement & refine-opt?
  36. Can you tape-out the chip with max-tran violation?
  37. You build clock tree for 500MHz, can we use the same for 400MHz clock without making any changes?
  38. What is UPF?
  39. How do hold fixing for reg to out path?
  40. How do you set uncertainty for interclock domain path?
  41. What is double patterning?
  42. What is an ICG? How do you model the fan-out of an ICG in synthesis?
  43. What is pipelining resistor?
  44. What is path group? How did you do path group?
  45. What is useful skew?
  46. What are the different types of NDR rules you used and how they affect the high frequency and low frequency networks
  47. What is skew group? What is top, trunk and leaf? What is transition value you give in that?
  48. How gating checks are done? Which is a better ICG according to you AND based one or OR based one.
  49. What are the challenges in placement and how to resolve the congestion at IO pins? Will you report it or you will fix it?
  50. Will LEC check is passed after scan-chain reordering?