Design for Testability (DFT)

Why DFT?

DFT is a structural way of testing which helps to detect faulty chip after fabrication by adding /designing anextra logic on circuit.

Designing an extra logic is a technique / methodology to satisfy controllable, observable, Test time, Test data, Test coverage, Fault coverage and ISO requirements.

Course overview - DFT

14 weeks program

8 hours class classroom session

Every topics and subtopics are discussed in detail with practical aspects and hands-on sessions

Our designs are co-developed with inputs from industry experts

Regular assessment test to identify the areas that candidate needs to improve

Enable learning through regular theory and labs assignment

Course completion Certificate after successful completion of the program

Trainer - DFT

Trainer has 8+ years of experience in semiconductor industry, comes with a great technical background in ASIC, especially inDFT.

Worked on different projects with different DFT specifications in block, sub-system and Chip level.

Experience on DFT involved in various stages from specifications, design, development, implementation, signoff & ATE Testing stages.

Strong Experience in pre and post silicon activities.

Worked in RTL, DFT and STA.

Experience in people guiding / training in various stages & currently leading a team.

Strong hands on experience in various industry tools.

Strong in scripting languages like PERL, TCL etc.,

Work efficiency and time saver comes through scripting. Hands on experience in DFT scripting.

Trainer 1

Syllabus - DFT

Module 1: Introduction to Digital design & Linux commands.

Module 2: Introduction to ASIC, Importance of ASIC & ASIC Flow.

Module 3: Introduction toDFT. Importance of DFT.

Module 4: DFT Flow, Inputs required for DFT.

Module 5: DFT Methodologies / Techniques, Design rule checks analysis & fixing, Insertion Flow.

  •   Internal SCAN / Normal SCAN, Internal SCAN pros & cons.
  •   SCAN Compression techniques.
  •   OCC.
  •   P1500.
  •   JTAG.
  •   Hierarchical SCAN.

Module 4: ATPG / Pattern generation, Design rule checks analysis & fixing, Pattern generation Flow.

  •   Introduction of ATPG.
  •   Fault models.
  •   Fault categories & classes.
  •   Test coverage & Fault coverage.
  •   Test coverage improvement analysis.

Module 3: Simulations.

  •   NO-Timing & Timing.
  •   Simulation debug.

Module 3: TCL scripting.

Module 3: STA basics.

Module 3: Final projects (Multiple).

Labs - DFT

  •  SCAN Insertion Flow
    •   SCAN DRC Analysis
    •   SCAN DRC fixing
    •   Internal Scan insertion
    •   SCAN Compression Insertion
    •   OCC insertion
    •   Wrapper insertion
  •  ATPG Flow
    •   ATPG DRC Analysis
    •   ATPG DRC fixing
    •   Pattern generation for stuckat
    •   Pattern generation for transition-> LOC
    •   Pattern generation for transition-> LOS
    •   Pattern generation for transition-> LOES
    •   Pattern generation for path-delay
    •   Coverage improvement analysis
    •   GLS No-Timing
    •   GLS Timing
    •   Simulation debug

Who can attend - DFT

  •  Engineering Graduates (BTech, BE, BS)
  •  Engineering Post-Graduates (MTech, ME, MS)
  •  Experienced Engineers who want to improve their domain to DFT
  •  College faculties who want to gain industry knowledge