Design Verification (DV)

Why DV?

Design verification is combination of both digital design and advanced verification technologies. It's a combination of HDL and HVL for RTL design and performs verification using advanced technologies like UVM & Python based scripts.

Course overview – DV

16 weeks program

Program covers all the aspects of Gate-Level to Netlist

Covers modules like Advanced Digital Design, Advanced Verilog coding, FSM modules, Memories, OOPS, System-Verilog concepts, Randomizations, Assertions, Test-bench environment creations and Scripting

Course module is framed by Semiconductor industry veterans

Trainer – DV

Trainer has 10+ years of vast experience in both industry and academia

Strong Hands-on experience in the area of digital design, RTL coding, FPGA/ASIC architecture definitions, Algorithmic level implementation in Altera (Intel) & Xilinx FPGAs

Have held various positions in industry like Design verification engineer & FPGA design engineer

Worked in ISRO as a Research Assistant in the CHIP Design Group

Trained 300+ fresh graduates & engineering professionals across the globe

Trainer 1

Syllabus – DV

Module 1: Introduction about VLSI technology

Module 2: Digital design

Module 3: Advanced Digital design

Module 4: Introduction to Verilog-HDL

Module 5: Verilog HDL program construct

Module 6: Task & function, Modeling Techniques, Timing control, Timing checks

Module 7: Data types, Arrays, Queue, Structure, Unions

Module 8: System Verilog, Mailbox & Packages, Randomization & constraints

Module 9: Assertion basics

Module 10: UVM introduction, Factory overrides, UVM reporting

Module 11: TLM

Module 12: UVM diver, sequencer, monitor, agent, environment

Module 13: Register Abstraction Layer (RAL)

Module 14: Functional Coverage model & Subscriber

Module 15: Reference model

Module 16: Real time projects with advanced protocols to build candidates professional expertise

Labs – DV

  •  Real time projects involving AMBA, AXI, USB, PCI advanced protocols

Who can attend – DV

Engineering Graduates (BTech, BE, BS)

Engineering Post-Graduates (MTech, ME, MS)

Experienced Engineers who want to change their domain to Design Verification

Experienced Engineers who want to improve their Design Verification skills

College faculties who want to gain Industry knowledge