Physical Design (PD)

Why PD?

Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.

Course overview - PD

15+ week program

Program covers all aspects of Netlist2GDS flow

Every topic and sub-topics are discussed in detail with practical aspects and hands-on sessions

Covers advanced concepts in Digital Design, CMOS, PnR flow, Signoff STA, Physical Verification, Low Power methodologies, Logic Equivalence Check and TCL scripting

Our designs are co-developed with inputs from industry experts

Soft Skill training

Resume preparation support

Regular assessment test to identify the areas that candidate needs to improve

Enable learning through regular theory and Labs assignments

Course completion Certificate after successful completion of the program

The path to industry would be very clear once this program is successfully completed

Labs can be accessed through VPN (24x7) from anywhere



Physical Design PD vlsi

Trainer 1 - PD

Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA

Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc

Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups

Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures

Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies

500+ Engineers have been trained across the globe

Trainer 1
ABOUT US

Trainer 2 - PD

Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts

Executed Full Chip, Sub-System and block levels creating partitions

Have worked on Signoff like STA, PV, IR etc.

Experienced with 6 years in training who has held various levels of trainings

Trained about 650+ engineers

Trainer brings in experience from multiple MNCs with about 16+ years of industry experience

Trainer is leading a team of 60+ engineers currently

Working on Full Chip and methodology development

Technology node expertise from 7nm till 250nm across various foundries

Strong hands on experience in Synopsys and Cadence tool sets

Strong in TCL and PERL

Syllabus - PD

  •   Module 1: Advanced Digital Design
  •   Module 2: Introduction of CMOS Circuits
  •   Module 3: Introduction to Physical Design Flow & Inputs
  •   Module 4: Design Planning (Floor-plan)
  •   Module 5: Power-Routing
  •   Module 6: Static Timing Analysis
  •   Module 7: Pre-Placement & Std-Cell Placement
  •   Module 8: Timing Optimization
  •   Module 9: CTS & Post-CTS Timing Optimization
  •   Module 10: Routing
  •   Module 11: Sign-off Checks
  •   Module 12: Timing Closure & ECO Implementation
  •   Module 13: Low-Power Implementation
  •   Module 14: Introduction to Advanced STA Topics
  •   Module 15: TCL Scripting
  •   Module 16: Final Projects ( Multiple )

Labs - PD

  •  Complex block level implementation
  •  Multiple designs covering full PnR end to end

EDA Tools and Projects - PD

    .
  •  Most prominent and widely used tools in the industry
  •  Multiple Projects including CPU Cores

Who can attend - PD

  •  Engineering Graduates (BTech, BE, BS)
  •  Engineering Post-Graduates (MTech, ME, MS)
  •  Experienced Engineers who want to change their domain to Physical Design
  •  Experienced Engineers who want to improve their Physical Design skills
  •  College faculties who want to gain Industry knowledge