Physical Design (Level-1)

Why PD?

Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.

Course overview - PD (Level-1)

12 weeks program

Program covers all aspects of Netlist to GDSII flow (refer syllabus for Level-1)

Every topic and sub-topic covers industry oriented practical aspects

Every topic and sub-topic is taught with hands-on lab from NL to GDSII

Coverage of topics like Advanced Digital Design, CMOS, PnR flow, Sign-Off STA, Physical Verification, TCL are key differentiators in the program

This program is primer program for entrants to VLSI industry

Curriculum and projects are co-developed with inputs from Industry experts

Soft skill training on the fly during the sessions

Resume preparation guidance

Regular assessment of areas where program members need improvement within scope of Level-1 program

In depth learning by interlinked theory and labs in parallel for NL2GDSII flow

Course completion certificate after completion of the program

Trainers and Mentors available anytime for discussion

Initial step to enter VLSI industry will be clear once this program is completed

Labs can be accessed 24x7 through VPN from anywhere

Trainer 1 - PD

Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA

Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc

Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups

Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures

Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies

500+ Engineers have been trained across the globe

Trainer 1

Trainer 2 - PD

Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts

Executed Full Chip, Sub-System and block levels creating partitions

Have worked on Signoff like STA, PV, IR etc.

Experienced with 6 years in training who has held various levels of trainings

Trained about 650+ engineers

Trainer brings in experience from multiple MNCs with about 16+ years of industry experience

Trainer is leading a team of 60+ engineers currently

Working on Full Chip and methodology development

Technology node expertise from 7nm till 250nm across various foundries

Strong hands on experience in Synopsys and Cadence tool sets

Strong in TCL and PERL

Syllabus - PD (Level-1)

  •   Module 1: Advanced Digital Design & CMOS fundamentals
  •   Module 2: Introduction to Physical Design Flow & Inputs
  •   Module 3: Introduction to Linux Operating System
  •   Module 4: Design Planning (Floorplan)
  •   Module 5: Power-Routing
  •   Module 6: Static Timing Analysis fundamentals
  •   Module 7: Pre-Placement & Std-Cell Placement
  •   Module 8: Timing Optimization
  •   Module 9: CTS & Post-CTS Optimization
  •   Module 10: Routing
  •   Module 11: Sign-off STA Checks on STA tool
  •   Module 12: Timing Closure & ECO Implementation
  •   Module 13: Physical Verification Checks
  •   Module 14: TCL Scripting for design aspects
  •   Module 15: Final Project

Labs - PD (Level-1)

  •  Complex block level implementation
  •  Multiple designs covering full PnR end to end

EDA Tools and Projects - PD (Level-1)

  •  Most prominent and widely used tools in the industry
  •  Multiple Projects including CPU Cores

Who can attend - PD (Level-1)

  •  Engineering Graduates (BTech, BE, BS)
  •  Engineering Post-Graduates (MTech, ME, MS)
  •  Experienced Engineers who want to change their domain to Physical Design
  •  Experienced Engineers who want to improve their Physical Design skills
  •  College faculties who want to gain Industry knowledge