Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.
12 weeks program |
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Program covers all aspects of Netlist to GDSII flow (refer syllabus for Level-1) |
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Every topic and sub-topic covers industry oriented practical aspects |
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Every topic and sub-topic is taught with hands-on lab from NL to GDSII |
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Coverage of topics like Advanced Digital Design, CMOS, PnR flow, Sign-Off STA, Physical Verification, TCL are key differentiators in the program |
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This program is primer program for entrants to VLSI industry |
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Curriculum and projects are co-developed with inputs from Industry experts |
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Soft skill training on the fly during the sessions |
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Resume preparation guidance |
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Regular assessment of areas where program members need improvement within scope of Level-1 program |
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In depth learning by interlinked theory and labs in parallel for NL2GDSII flow |
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Course completion certificate after completion of the program |
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Trainers and Mentors available anytime for discussion |
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Initial step to enter VLSI industry will be clear once this program is completed |
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Labs can be accessed 24x7 through VPN from anywhere |
Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA |
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Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc |
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Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups |
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Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures |
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Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies |
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500+ Engineers have been trained across the globe |
Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts |
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Executed Full Chip, Sub-System and block levels creating partitions |
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Have worked on Signoff like STA, PV, IR etc. |
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Experienced with 6 years in training who has held various levels of trainings |
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Trained about 650+ engineers |
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Trainer brings in experience from multiple MNCs with about 16+ years of industry experience |
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Trainer is leading a team of 60+ engineers currently |
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Working on Full Chip and methodology development |
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Technology node expertise from 7nm till 250nm across various foundries |
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Strong hands on experience in Synopsys and Cadence tool sets |
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Strong in TCL and PERL |
