Trainer 1

Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA

Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc

Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups

Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures

Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies

500+ Engineers have been trained across the globe

Trainer 1
ABOUT US

Trainer 2

Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts

Executed Full Chip, Sub-System and block levels creating partitions

Have worked on Signoff like STA, PV, IR etc.

Experienced with 6 years in training who has held various levels of trainings

Trained about 650+ engineers

Trainer brings in experience from multiple MNCs with about 16+ years of industry experience

Trainer is leading a team of 60+ engineers currently

Working on Full Chip and methodology development

Technology node expertise from 7nm till 250nm across various foundries

Strong hands on experience in Synopsys and Cadence tool sets

Strong in TCL and PERL